This section introduces aspects that may help facilitate a better understanding of the invention. Accordingly, the statements of this section are to be read in this light and are not to be understood as admissions about what is prior art or what is not prior art.
Scan testing is used by integrated circuit (IC) manufacturers to determine structurally whether or not there are any manufacturing defects in the integrated circuit. During scan testing, external automated test equipment (ATE) configures a chip into a scan-test mode that provides access to monitor the internal processing of the chip's core logic, e.g., by making intermediate processing results available outside of the chip's logic. Depending on the particular implementation, the input data applied to the chip's core logic during scan testing may be provided by the ATE or by special on-chip BIST (built-in self testing) circuitry. Similarly, depending on the particular implementation, the intermediate processing results from the chip's core logic may be transmitted to the ATE for evaluation or may be evaluated by the on-chip BIST circuitry to determine whether or not the chip's core logic has a manufacturing defect.
In many situations, it is desirable to restrict access to a chip's scan-test mode. For example, a chip manufacturer may want to prevent its customers from performing scan testing on its chips in order to preserve confidential information regarding the internal processing by those chips. It is also desirable to provide scan testing that is capable of testing as much of a chip's core logic as possible.